Venkatesh Pamidi
Physical Design Engineer at SiFive Inc
- Role
- Physical Design Engineer at SiFive
- Location
- Portland, OR, US
- LinkedIn followers
- 500 followers
About Venkatesh Pamidi
I’m a motivated and detail-oriented Physical Design Intern currently contributing to the…
Experience
Physical Design Engineer
Oct 2024 — Present · Portland, OR, US
Physical Design Engineer – RISC-V Processor ImplementationContributing to the physical implementation of RISC-V processor cores at advanced nodes (7nm/5nm), with hands-on experience in floorplanning, placement, and Clock Tree Synthesis (CTS) across multiple blocks. Responsible for Static Timing Analysis (STA) and timing closure using PrimeTime, addressing setup/hold violations through targeted ECOs. Collaborating with senior engineers to resolve congestion challenges, optimize block utilization, and improve power and ground network planning. Gaining exposure to Design for Test (DFT), Logic Equivalence Checking (LEC), and power intent management via UPF/CPF.Tools & Skills: Synopsys ICC2, Design Compiler, PrimeTime, Cadence Innovus, TCL, Python.
Education
Tirumala Engineering College
Bachelor of Technology - BTech, Electronics and Communications Engineering
Portland State University
Master of Science - MS, Electrical and Computer Engineering
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