Venkatesh Pacchipulusu
Analog Design Engineer
- Role
- Analog Design Engineer at Synapse Design Inc
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Venkatesh Pacchipulusu
I have 3+ years of experience in the analog domain. Working on serdes projects like DDR, clocking phy,Level shifters, LDO and BGR (TSMC 3nm,5nm,16nm and 40nm). clients as an Intel,Rambus,Renesas,Hygeiasemi etc. Skills on cadence virtuoso,mastero.
Experience
Analog Design Engineer
May 2022 — Present · Hyderabad, IN
worked on clocking buffers in DDR memory phy (TSMC-5nm) client as Rambus
Education
Lingayas Institute of Management & Technology, Vijayawada , PIN-521212(CC-NA)
Bachelor of Technology - BTech
2013 — 2017
Lahari vidya mandir
Bachelor of Technology - BTech
2013 — 2017
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.