Venkatesh Nayak

Senior Director of Engineering @高通

San Diego, CA, US

EMAILS

v•••••@qualcomm.com

MOBILE NUMBERS

+18•••••••30

Reveal Contact Details

Signup · Get unlimited contacts

WORK HISTORY

Nov 2025 — Present

Senior Director of Engineering @高通

View department →

San Diego, CA, US

EDUCATION

1990 — 1992

Sri Bhuvanendra College Karkala

PUC, PCMB

1992 — 1996

SDM college of Engg. and Tech, Dharwad

BE (E&E), Electrical and Electronics Engineering

1988 — 1990

GPUC Bailur

High School

SKILLS

TclFunctional VerificationPhysical DesignTiming ClosureSemiconductorsStatic Timing AnalysisIcApplication-Specific Integrated Circuits (Asic)Vlsi Physical DesignIntegrated Circuit DesignVlsiAsicSystem on a Chip (Soc)SocLow-Power DesignVery-Large-Scale Integration (Vlsi)Integrated Circuits (Ic)EdaPrimetimeVerilog

ABOUT VENKATESH NAYAK

Over 20+ years of Semiconductor industry experience. Leading experience in Physical Design Tapeouts.Physical design PD lead role for SOC chip, Modem and CPU sub systems.Managed global CPU PD teams. Driving the core PPA improvements and T/O executions.Providing technical guidance to the team members.ARM core CPU subsystem PD implementation in latest Nano Technologies.Latest technology enablement for PPA and QoR improvements.Worked on multiple in-house projects at Intel, Texas Instruments and NPTest.

This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.