Venkatesh Nandyala
AMS Layout Engineer at Synopsys Inc
- Role
- Layout Design Engineer at Synopsys Inc
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Venkatesh Nandyala
Worked on TSMC 2nm, 3nm,5nm,7nm,28nm and, GF45nm in Planar & FINFET technologies.+Hands on experience in Analog & Mixed signal layouts.+Worked for AMD and Vidatronics clients.+Good Knowledge on Matching of Devices in current mirrors, diff pairs and op-amp designs.+Proper knowledge on signal flow, Power/ground structure, Floor planning.+Good Knowledge on Layout concepts like Latch-up, WPE, LOD, Shielding, EM & IR, ESD,Antenna violation.+Hands on experience in analog blocks (SerDes, LDO, BGR, VCO), Memory blocks (Cram), I/O blocks (Level shifter, GPIO, mux).+Efficient in debugging DRC, LVS related verification issues.+Communicating with Analog designers for reviewing and suggesting for a better layout.
Experience
Layout Design Engineer
Nov 2024 — Present · Hyderabad, IN
Education
Bapatla Engineering College
Bachelor of Technology - BTech
2016 — 2020
Bapatla Polytechnic College
Diploma
2013 — 2016
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