Venkatesh Kulkarni
Formal Engineer
- Role
- Principal Engineer at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Venkatesh Kulkarni
A seasoned design verification professional with ~13 years of experience (7 years in Formal Verification (FV) and 5 years in simulation).• Expert in developing formal test benches from scratch.• Strong ability to analyze designs and assess their suitability for Formal Verification.• Proficient in test planning—creating and executing comprehensive formal verification test plans.• Achieved significant left-shift verification through formal methodologies, improving efficiency.• Uncovered multiple extreme corner-case bugs using formal verification, preventing potential silicon escapees.• Deep expertise in formal sign-off, reachability analysis, convergence, complexity handling, bug hunting, COI, and proof core analysis.• Proficient in industry-leading tools: JasperGold FPV, SEC, and Superlint.• Skilled in SystemVerilog, SVA, Tcl, and Perl scripting.• Key contributor to team expansion, helping scale a formal verification team from 2 to 15 members.• Collaborated closely with principal formal engineers and automation teams to drive methodologies such as unit qualification, gatekeeper/weekly regression, coverage closure, auto-checks, liveness checks, and formal sign-off criteria.• Good understanding of x86 core architecture and power management units.
Experience
Principal Engineer
Jun 2025 — Present · Bengaluru, IN
Working on reproduction and fix validation on customer sightings in the Ethernet MAC layer- Reactive formal.• Formal testbench development from scratch for Ethernet PHY layer-Proactive formal
Education
PDA college of Engineering,Gulbarga
B.E, Electronics & Communication
2005 — 2009
Bangalore Institute of Technology
M.Tech, VLSI & Embedded systems
2009 — 2011
Skills
- Perl
- Embedded Systems
- Eda
- Verilog, System Verilog, Uvm,Perl, Cshell,Tkl
- Lte
- Vlsi
- Integrated Circuit Design
- Modelsim
- Debugging
- Rtl Design
- Digital Electronics
- Functional Verification
- Matlab
- Arm
- Verilog
- Vhdl
- Processors
- Soc
- Microcontrollers
- Tcl
- Fpga
- Asic
- Xilinx
- Systemverilog
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