Venkatesh Kadimi
Senior Design Verification Engineer @NVIDIA
Santa Clara, CA, US
EMAILS
v••••••@nvidia.com
MOBILE NUMBERS
+19•••••••50
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WORK HISTORY
Jan 2020 — Present
Senior Design Verification Engineer @NVIDIA
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San Francisco, CA, US
EDUCATION
2009 — 2013
Birla Institute of Technology and Science, Pilani
Bachelor of Engineering (B.E.), Electronics and Instrumentation Engineering
2016 — 2018
North Carolina State University
Master of Science (MS), Computer Engineering
SKILLS
CMatlabLinuxProgrammingVerilogField-Programmable Gate Arrays (Fpga)Embedded SystemsXilinx IseCadence VirtuosoRtl DesignDebuggingDigital Circuit DesignModelsimSynopsys ToolsStatic Timing AnalysisC++
ABOUT VENKATESH KADIMI
Working as a Design Verification Engineer in CPU memory subsystem team and responsible for development and maintenance of UVM based testbench, Assertion based Verification, Coverage Test plan and closure. Hands on experience in RTL design and all stages of verification cycle for a project - test planning, test bench development, debugging RTL simulation, coverage closure.
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