Venkatesh Jayanti
Silicon Engineer @Google
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WORK HISTORY
Silicon Engineer @Google
Bengaluru, IN
Working as a SOC DFT Engineer.
EDUCATION
Indian Institute of Technology, Kanpur
Master of Technology - MTech, Microelectronics and VLSI
Indore Public School
12th, PCM
Indian Institute of Technology, Indore
Bachelor of Technology - BTech, Electrical and Electronics Engineering
Atomic energy central school, Indore
10th
ABOUT VENKATESH JAYANTI
DFT Engineer @Google. Experienced in IJTAG, Scan Architecture, ATPG pattern generation and simulation, with Good debugging skills in popular EDA tools from different vendors such as Siemens and Cadence. Good knowledge of Verilog/SystemVerilog. Strong communication skills. Also have some experience in Design Verification tasks within the DFT domain with some background in Formal Verification. M.Tech in Microelectronics and VLSI from IIT Kanpur, and B.Tech in Electrical Engineering from IIT Indore. Excellent communication skills, with spoken fluency in 3 languages: English, Hindi, and Telugu.
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