Venkataramanan Srinivasan

WORK HISTORY

EDUCATION

SKILLS

ABOUT VENKATARAMANAN SRINIVASAN

Driven by a passion for automation and efficiency in semiconductor design, my career has been a journey of pioneering CAD methodologies that revolutionize chip design, verification, and optimization. With over 19 years of experience, I have built and led high-impact engineering teams, architected industry-leading design flows, and introduced automation that drastically reduces silicon development cycles. I am dedicated to enhancing quality, speed, and automation in semiconductor CAD methodologies. I thrive on developing scalable, technology-agnostic solutions that streamline RTL-to-Tapeout processes, reduce design iterations, and improve silicon quality. – Reducing turnaround times by 6-20 weeks per SoC project through automated GLS collateral generation, PPA regression, and milestone quality tracking, resulting in multimillion-dollar savings for the corporation. – Partnering with global teams across RTL, DV, DFT, PD, IP, and EDA vendors to standardize workflows and eliminate integration inefficiencies. – – Leveraging in-depth analytics to optimize power, performance, and area (PPA) metrics, enhancing silicon efficiency. – Recipient of 25+ peer recognition awards and Innovation Champion awards, and a panel judge at industry conferences like SNUG and CDNLive. & – Improving solution usage quality and increasing productivity beyond targets.From Google to Infineon and Cypress, my work has directly influenced CAD flow strategies across leading semiconductor organizations. I am passionate about tackling complex design challenges, mentoring the next generation of engineers, and shaping the future of VLSI automation. ’! Reach me at j••••••••@gmail.com.