Venkatakrishna Dusetty

About Venkatakrishna Dusetty

Yield Development Engineer, Low Yield Analysis Debug Lab, Intel Corporation, Hillsboro, Oregon.Yield Development Engineer with 5+ years of experience in advanced Fault Isolation (FI) and Failure Analysis (FA) across advanced semiconductor technologies. Proven expertise in semiconductor devices, electrical, optical, and thermal FI techniques and demonstrated success in leveraging diagnosis data, layout analysis, and cross-functional collaboration with nanoprobing and imaging teams to identify root causes and drive yield improvements. Recognized with multiple divisional awards for impactful contributions to low-yield analysis and process development.Skills: Fault Isolation, Failure Analysis, Scanning Electron Microscopy (SEM), Semiconductor Process Technology, Transmission Electron Microscopy (TEM), Defect Identification, Data Analysis, Infrared Emission Microscopy (IREM), Lock-in Thermography (LIT), Scan Diagnosis, Interpretation of Nanoprobing Data, Optical Beam Induced Resistance Change (OBIRCH), Thermal-assisted Device Alteration (TADA), Laser Timing Module (LTM), Laser Voltage Probe (LVP).

Experience

1. Yield Development Engineer

   Intel

   May 2020 — Present · OR, US

   Responsible for debugging Intel client and server products to achieve yield learning for the technology development of next generation semiconductor technologies (10 nm, 7 nm and Intel 18A)Experienced in utilizing Electrical FI techniques, Optical FI techniques such as Infrared Emission Microscopy (IREM), Laser Timing Module (LTM), Laser Voltage Probe (LVP), and Thermal FI techniques such as Lock-in Thermography (LIT), Optical Beam Induced Resistance Change (OBIRCH), Thermal-assisted Device Alteration (TADA) in conjunction with test pattern modification to obtain quick and reliable FI data Parametric, Scan, Array, and Functional debugSpecialized in analyzing fault isolation data, tessent diagnosis files, layout analysis, and latest process knowledge to guide a sample through failure analysis for the determination of root cause by partnering with Nanoprobing and TEM EngineersExperienced in nanoprobing data analysis, reviewing layer by layer inspection data, Scanning Electron Microscope (SEM) images, Transmission Electron Microscope (TEM) images, and Energy-dispersive X-ray (EDX) data looking for any abnormalitiesPerformed New Product Introduction (NPI) of multiple Intel products on existing FI platforms, driving strategic evaluation and enablement of debug capabilitiesServed as backup tool owner for Thermal FI tool, collaborating with vendors and Field Service Engineers to design experiments and develop methodologies that significantly improved tool capability and throughput of Thermal FI techniques. Trained new users on comprehensive tool operation, including setup, troubleshooting, and best practices to ensure efficient usageReceived 8 Quarterly Divisional Awards for outstanding contributions in debugging, identifying failure modes, and delivering critical results to update Defect Pareto of multiple process technologies Hands-on experience working with hardware and test equipment. Proficient in data handling and statistical analysis on JMP software

Education

• Jawaharlal Nehru Technological University, Anantapur

  Bachelor of Technology (B.Tech.), Electrical and Electronics Engineering

  2011 — 2015

• University of Massachusetts Amherst

  Master's degree, Electrical and Computer Engineering

  2016 — 2020

Skills

• Microsoft Word
• Matlab
• Research
• Semiconductors
• Leadership
• Python
• Microelectronics
• Simulink
• Semiconductor Fabrication
• C
• Cadence Virtuoso
• Microsoft Office
• Laboratory Experience
• Vlsi Cad
• Management
• Powerpoint
• Microsoft Excel
• Training