Venkata Sai Vamshi Kulluru
Physical Design & Verification Trainee @Maven Silicon
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WORK HISTORY
Physical Design & Verification Trainee @Maven Silicon
Physical Design- Executed complete Physical Design flow from synthesized netlist through floorplanning, placement, CTS, and routing- Performed static timing analysis (setup/hold), slack analysis, and timing closure- Analyzed congestion and optimized routing resources to meet PPA goals- Gained practical exposure to clock tree synthesis, signal integrity, and DRC/LVS awarenessFunctional Verification- Developing SystemVerilog-based verification environments- Writing assertion-based checks using SystemVerilog Assertions (SVA)- Working with verification planning, functional coverage, and debug methodologies
EDUCATION
University of North Carolina at Charlotte
Master of Science - MS, Electrical Engineering
Amrita Vishwa Vidyapeetham
Bachelor of Technology - BTech, Electrical and Electronics Engineering
ABOUT VENKATA SAI VAMSHI KULLURU
VLSI-focused Electrical Engineer with hands-on experience in RTL design, Physical Design, and Functional Verification.Trained at Maven Silicon, with practical exposure to the complete Physical Design flow including floorplanning, placement, CTS, routing, congestion analysis, and timing closure. Currently working on SystemVerilog-based functional verification including testbench architecture, assertions (SVA), and coverage concepts.Strong academic foundation in CMOS VLSI and digital systems through an MS in Electrical Engineering from UNC Charlotte. Experienced in Verilog/SystemVerilog, STA, FSMs, and RTL debug. Prior industry experience at Infosys strengthened my engineering discipline, documentation, and root-cause analysis skills directly applicable to silicon bring-up and verification environments.Actively seeking entry-to-mid level roles in:• RTL Design• Physical Design• Functional Verification
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