Venkata Surendra Amara

About Venkata Surendra Amara

Responsible for Block level Floorplanning, Power planning, DeCap insertion, Placement Driven Synthesis, Post placement Timing closure, Clock Tree Synthesis, Clock wiring, Post clock Timing closure, clock slew fixing, late mode optimization (Set-up Fixing on prewired database), Early mode optimization (Hold fixing on prewired database), Timing driven and SI driven Routing,Post Route Timing fixing, Fixing DRCs.Specialties: Areas‐Partitioning, IO ring preparation, Floor planning, PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR drop analysis, Physical verification, Signal Integrity, Low Power design

Experience

1. Senior Staff Engineer Manager

   Qualcomm

   Dec 2023 — Present · Bengaluru, IN

Education

• Ratnam Residential High School, Nellore, AP

  9-10th Class, As Follows

  2003 — 2005

• Siddhartha English Medium School, Nellore, AP

  Till 8th-Class, Telugu, Hindi, English, Maths, Science, Social

  1993 — 2003

• Vidya Jyothi Institue of Technology, Hyderabad, AP

  B.Tech (JNTU), Electronic & Communication Engineering

  2007 — 2011

• Narayana Junior College, Nellore, AP

  Intermediate, Maths, Physics & Chemistry

  2005 — 2007

Skills

• Tcl
• Timing
• Static Timing Analysis
• Drc
• Low-Power Design
• Floorplanning
• Place & Route
• Physical Verification
• Logic Synthesis
• Timing Closure
• Asic
• Vlsi
• Signal Integrity
• Physical Design
• Clock Tree Synthesis