Venkata Siva Reddy
Smts Silicon Design Engineer @AMD
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WORK HISTORY
Smts Silicon Design Engineer @AMD
Bengaluru, IN
SKILLS
ABOUT VENKATA SIVA REDDY
More than 14 years of experience in physical design methodologies through Graphic chips & & PCI Express Switches.Targeted for desktop and mobile applications at 65nm,45nm and 28nm, 14nm, 7m technologiesHandled complex blocks in various successful Tape-outs with Multi million gates.Experienced in floorplanning, placement and optimization for timing closure, clock network planning, power distribution planning and routing at block level.Knowledge of static timing analysis concepts for both block level and top-level.Strong knowledge in signal integrity issues such cross-talk, EM and IR drop.Working knowledge of low power methodologies and impact on overall design goals.Knowledge of post layout physical verification and DFM rules.Specialties: P & & R Tools : SOC-FE (Cadence), Aprisa (Atoptech),IC- Compiler (Synopsis), Sierra Pinnacle (Mentor Graphics)Extraction Tools : Star-RCTiming Analysis Tools : Primetime (PT), Encounter Timing System (ETS) Cross-Talk Analysis Tools : PT-SIPhysical Verification Tools : Caliber(Mentor Graphics)ASIC Synthesis Tools : DC-Compiler (Synopsis)Scripting Languages : Perl, SED, TCL, AWK
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