Venkata Rajesh M.
ML Implementation Engineer @ Meta | MBA, VLSI
- Role
- Hardware Engineering Lead at Meta
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Venkata Rajesh M.
As an ML Implementation Engineer at Meta, I work on designing and optimizing hardware solutions for Facebook Reality Labs, the division that creates cutting-edge products and experiences in augmented and virtual reality. With over 6 years of experience in hardware engineering and machine learning, I am passionate about solving difficult problems and achieving success for the team.I have a strong educational background in electrical and electronics engineering, computer engineering, and business administration, with multiple degrees and certifications from reputed institutions. I also have a keen interest in VLSI engineering, coding, and computer science, and I have published a paper on ISPD-2010, a prestigious conference on physical design. I am always eager to learn new things and expand my knowledge and expertise in the field of hardware and ML. I value creativity, collaboration, and positive attitude in my work.
Experience
Hardware Engineering Lead
Jul 2021 — Present · Sunnyvale, CA, US
Facebook Reality Labshttps://about.meta.com/realitylabs/As a Hardware Engineering Lead in the Machine Learning IP team at Facebook Reality Labs, I delivered ML IP for low power applications using a vendor-based model. I worked with Samsung and TSMC based design service partners to integrate the IP into SoCs for AR applications. I owned all aspects of implementation, including partitioning, floorplanning, timing constraints, UPF, PD recipes for extreme low power, STA, Power analysis, and Dynamic IR analysis. I introduced various low-power strategies such as saif-based dynamic power optimization, TT corner optimization, customized floorplan, dataflow planning, VT strategies, CCD optimization, and recipes for dynamic IR mitigation. I worked closely with the RTL team to close timing, congestion, and achieve higher utilization while also working with vendors to unblock their issues, correlation, and tapeout the chip within schedule. I enabled regressions to provide RTL feedback, generate collateral for milestone drops to the vendor, adapt to changes in product roadmap, and converge QoR and recipes for ML IP throughout the product development cycle.
Education
University of California, Santa Cruz
Certification, VLSI Engineering, Computer Science
2013 — 2018
Coursera
Master's degree, Mathematics and Computer Science
2017 — 2019
University of Illinois Urbana-Champaign
Master of Business Administration - MBA, Business Administration and Management, General
Stanford University
Continuing Education, Computer Science
2017 — 2021
Birla Institute of Technology and Science, Pilani
Bachelor of Engineering (B.E.), Electrical and Electronics Engineering
2002 — 2006
Texas A&M University
M.S., Computer Engineering
freeCodeCamp
Coding
2017
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