Venkata R Immaneni

About Venkata R Immaneni

Senior Leader with over 37 years of experience at Intel with career recognition as…

Experience

1. Vice President

   Intel

   Sep 1984 — Present · Phoenix, AZ, US

   INTEL CORP, AZ 2010 – Present Sr. Director of Engineering, TMG/ TDArchitected, developed, and deployed PDKs, digital and custom reference design flows on over 20 different Intel process technologies for Intel design teams, and to external foundry customers and IP suppliers• Drove the integration of PDKs into multiple design systems at Intel• Partnered with EDA vendors and other Intel groups to drive the PDK defects down by 3x from 2019 • Increased the EDA tool breadth to 2x and on track to achieve 3x by 2022INTEL CORP, AZ – 2010 Director of Engineering, ICG/ MGDeveloped and deployed industry standard design flows, std cell libraries, memory compilers and basic IPs to all groups which are not designing micro-processors at Intel. Over 100 products have successfully taped out using the flows and collaterals developed by the group• Developed and deployed first High-Density Libraries at Intel (IAA, 2003)• Architected and developed first Memory Compilers at Intel (IAA, • Introduced and deployed IP reuse methodology at Intel• Served on Board for 3 EDA companies representing (Intel capital investments)INTEL CORP, AZ 1990 – Engineering Manager, WCCG/ CLEDeveloped first ASIC design flows at Intel. Drove replacement of internally developed tools with industry standard EDA formats and tools (VHDL, Verilog, Design Compiler, Calibre). • Introduced “Design Pipeline” concept. Managed design team responsible for implementation of successful tape-ins of over ten ASIC/ SoC designs • Designed and implemented the first synthesizable IA core at IntelINTEL CORP, AZ 1984 – 1990 Sr. CAD Engineer, ASIC/ AMEDeveloped tools and flows in APR, physical verification, design for test, logic simulation, timing verification, ERCs, and RTL entry and simulation. • Trained at IBM Burlington on ASIC Gate Array flows. Developed first ever ASIC design flow at Intel (IAA 1990)

Education

• Osmania University

  Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

  1976 — 1981

• Indian Institute of Technology, Kharagpur

  Master of Technology (M.Tech.), Computer Engineering

  1981 — 1983

• University of Cincinnati

  Master of Science (MS), Computer Engineering

  1983 — 1984