Venkata Krishnan Srinivasan

About Venkata Krishnan Srinivasan

Actively looking for a career in Memory Circuit and Compiler Design, Layout Tiling, Characterization and Verification of memories. Explore new design methodologies in VLSI Digital design.I have 10+ years experience in SRAM design for HPC, STA using Nanotime, IR/EM analysis, Flow development for characterization, PPA Analysis

Experience

1. Sr Sram Design Engineer

   台積電

   Jul 2020 — Present · San Jose, CA, US

   Timing and Power Characterization for High Speed Single Port Compiler and 2 Port Register File Compiler for 3nm and 2nm technologies. IR and EM Analysis for Compiler memories and debug IR/EM failures in Layout.3. Setup and Run Timing and Noise simulations using Nanotime tool. Data Correlation between Characterized Liberty File and Nanotime NLDM to debug key setup time and hold time issues in memories. Analyze all the critical C-G and D-G paths.5. Setup and Run LVF simulations using the Cadence Liberate MX tool and analyze the data.Automation for IREM runtime status and data collection.

Education

• SASTRA University

  Bachelor of Technology, Electronics and Communication Engineering

  2006 — 2010

• Arizona State University

  MS, ELECTRICAL ENGINEERING; Electronic; Mixed Signal Circuit Design

  2010 — 2012

Skills

• Cadence Virtuoso
• System Verilog
• Mixed Signal
• Circuit Design
• Spice
• Modelsim
• C++
• System Verification
• Hspice
• Skill
• Cadence
• Java
• Tcl
• Filter Design
• Vhdl
• Python
• Verilog
• Matlab
• Perl
• C
• Memory Design
• Spectre
• Nanotime
• Calibre
• Very-Large-Scale Integration (Vlsi)
• Layout Tiling