Veman Gottam
Staff Engineer (Physical Design) at Qualcomm
- Role
- Asic Physical Design Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Veman Gottam
Expertise in ASIC Physical Design Implementation from Netlist to GDS II in 3nm, 4nm, 5nm, 7nm, 10nm and 14nm technology nodes. Tasks are Soc Partitioning, Floorplan, PNR and Signoff analysis (STA, Formal verification and Physical Verification -DRC/ERC/PERC/LVS/SOFTCHECK/DFY/XOR).Proficient in Synopsys-FC, ICC, ICC2, DC, Primetime and StarRC; Cadence First Encounter, Innovus & Virtuoso; Mentor Graphics- Calibre and Apache- Redhawk tools.
Experience
Asic Physical Design Engineer
Mar 2015 — Present · Bangalore, IN
Education
ZPSSM
SSC
2005 — 2006
NVBJC (SR)
Intermediate, MPC
2006 — 2008
VCE/ JNTUH
Master of Technology (M.Tech), VLSI SYSTEM DESIGN
2012 — 2014
VITS
Bachelor of Technology (B.Tech), E.C.E
2008 — 2012
Skills
- Modelsim
- Tanner Tools
- Static Timing Analysis
- Digital Electronics
- Application-Specific Integrated Circuits (Asic)
- Tcl Scripting
- Cadence First Encounter
- Asic Physical Design
- Questasim
- C
- Xilinx
- Systemverilog
- Physical Design
- Verilog
- C Programming Language
- Tcl
- Perl
- Cmos Fundamentals
- Microcontrollers
- System Verilog
- Logic Synthesis
- Very-Large-Scale Integration (Vlsi)
- Integrated Circuit Design
- Perl Scripting
- Vlsi
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