Veeresh Kuruva

About Veeresh Kuruva

I\'m a technologist looking opportunities that inclines with my naturaltalents,education,Experience.I have 4+ year\'s of experience as DFT Engineer and another 2.5 years experience in Teaching (Lecturer/Asst.Prof).TOP Skills & Hands-On Experience as below->MBIST: Hands-on MBIST Insertion, RTL & GLS Simulations, BIRA-Sims & Insertion on SMS MBIST (SynopsisTool), Novas Verdi & DVE, Hands-on GLS & SDF(Min & Max) Simulations (MBIST ) & Debugging Skills, Pattern/Vector Generations->MBIST Validation: Hands-on MBIST Validation (MBIST VAL) Tasks as 1.Pattern Generation. 2.Debug the Test cases simulations->currently working in VLSI-DFT Engineer, Domain in Semiconductor Industry, For presently client Qualcomm, I had worked for client Intel Technology->I\'m proficient in DFT Architecture & Improve Overall Test Quality Like DFT Insertion- Scan Insertion, ATPG, Debug/Resolve DRC issues, worked on \"Tessent Tool\",\"Synopsis Verdi Tool\"->understand DFT efforts at SoC/Core level & for flat /Hierarchical Scan Insertion->Performed scan Insertion, compression, Analyzed ATPG faults/Test Coverage, ATPG Simulation.SKILLS:MBIST, ATPG, SCAN, BS

Experience

1. Senior Hardware Engineer

   ACL Digital

   Jul 2025 — Present · Bangalore Urban, IN

   Promoted as Senior Hardware Engineer.

Education

• Brindavan Institute of technology & Scinence, Kurnool

  B.Tech, Electrical, Electronics and Communications Engineering

  2014 — 2017

• S.G.P.R govt polytechnic college.kurnool

  Diploma of Education, AEIE

• G.Pulla Reddy Engineering college (Autonomous), Kurnool

  M.Tech, VLSI&ES(Embedded Systems)

  2019 — 2021