Veeraraju Potta

About Veeraraju Potta

Senior Staff Engineer | ASIC Verification | DDR & System-Level DV Experienced verification leader driving successful closure of DDR subsystem DV across multiple chipsets through to silicon. Led a high-performing 15-member team, delivering robust verification strategies and execution. Core Expertise:LPDDR4/5/6 protocols and low-power verificationFunctional verification from planning to closure at module and system levelsCoverage-driven, constraint-random verification methodologyUVM, SystemVerilog, and C-based environment developmentImage processing, USB2.0/3.0, and mobile application processor IPsBus protocols: AXI3, AHB, APB, OCP

Experience

1. Senior Staff Manager

   Qualcomm

   Dec 2021 — Present · Bangalore Urban, IN

   Leading DDR Memory Controller and Low Power Verification InitiativesCurrently leading verification efforts for DDR memory controllers (LPDDR4, LPDDR5, LPDDR6) and low power features across multiple chipsets. Managing and mentoring a team of 15 engineers, driving technical excellence and cross-functional collaboration to ensure robust verification coverage and timely delivery. Focused on building scalable verification environments, optimizing power-aware test strategies, and fostering a culture of ownership and continuous learning.

Education

• Andhra University college of engg

  Bachelor of Engineering (BE), Electronics and Communications Engineering

  1999 — 2003

• Indian Institute of Technology, Kharagpur

  Master of Technology (MTech), Computer Engineering

  2003 — 2005

Skills

• Asic
• Arm Architecture
• Universal Verification Methodology (Uvm)
• Processors
• Microcontrollers
• Dynamic Random-Access Memory (Dram)
• Cmos
• Usb2.0
• Uvm
• Signal Processing
• Rtl Design
• Usb3.0
• Vlsi
• Systemverilog
• Verilog
• Debugging
• Amba Ahb
• Specman
• Functional Verification
• Arm
• Ncsim
• Modelsim
• Soc