Veera Satish Bhimanadula
Aspiring Analog Layout Design Engineer || Trained in Takshila VSLI Institutions || B-Tech (ECE)
- Role
- Takshila Institute of Vlsi Technologies at Technical Hub
- Location
- Kakinada Rural, AP, IN
- LinkedIn followers
- 500 followers
About Veera Satish Bhimanadula
I am passionate Analog Layout engineer to designed and optimized analog/mixed-signal…
Experience
Takshila Institute of Vlsi Technologies
Present
Education
Aditya College Of Engineering & Technology
BTech
2021 — 2024
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