Veera Arjunan

About Veera Arjunan

Active Power Management Verification Engineer specializing in low-power SoC verification for Automotive (ASIL-D), AI, and Mobile applications. Proven expertise in ARM Cortex-based power management subsystems, ensuring robust functionality in always-on domains. Led verification efforts for multi-power mode designs, power-state transitions, power-up/down sequences for safety-critical systems. Developed SAIF-based power analysis for ARM Cortex-M processors and implemented C-based verification infrastructure in multi-die automotive SoCs and Mobile SoCs.Spearheaded UVM-based testbench architecture, enabling faster test generation, and uncovered critical pre-silicon bugs through CDC, X-propagation, and GLS validation. Collaborated with power architects to define verification strategies, ensuring correct retention logic, power gating, and wake-up sequences. Passionate about functional safety, low-power verification to deliver first-time-right silicon. 3 years of experience in Post Silicon Validation of mixed signal ICs in various ATE platforms like Teradyne Ultra Flex, J750 and eagle tester, with good knowledge in reliable test solution bring up and test debug, PCB design and test hardware debug. Strong base knowledge in NI LABVIEW.

Experience

1. Staff Engineer

   Samsung Semiconductor

   Mar 2026 — Present · Bengaluru, IN

Education

• Mepco Schlenk Engineering College

  Engineer’s Degree, Electrical and Electronics Engineering

  2015 — 2019

• BITS Pilani Work Integrated Learning Programmes

  Master of Technology - MTech, VLSI Design and Microelectronics

• M.S.R Matriculation Higher Secondary School

  Higher secondary, Biology, Maths

Skills

• Microsoft Word
• Project Management
• C Programming
• Management
• Leadership
• Public Speaking
• Customer Service
• Research
• Microsoft Excel
• Powerpoint
• Microsoft Office