Veena P.
ASIC verification engineer at Capgemini
- Role
- Senior Consultant at Capgemini Engineering
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Veena P.
ASIC Verification engineer with 7+ years of VLSI Industry experience.Working in DDR -phy (DDR5PHY) IP. Worked in DDR5PHY protocol IP verification including side-band signals, alert feature, channel inactive verification, BL36, different configuration support etc. Worked in code and functional coverage and implemented some checkers test case for some feature verification. Experienced in developing UVM and SV testbenches from the scratch, experienced in developing verification components ( Env, Tests, Scoreboard) using System Verilog and UVM methodology.Hands on experience in IP verification of Video IP\'s ( Both Unit level and top level) from the scratch.Well versed in coverage closure, assertions and constrained random stimulus testingExperienced in different scripting languages like PERL,Shell, python Worked on VIP development of AXI-4Stream protocol.Experience in DDR,AHB, AXI 4 Stream,APB, AXI,I2C, IPC protocols
Experience
Senior Consultant
Feb 2026 — Present · Bengaluru, IN
Education
Government Engineering College, Kozhikode
Bachelor of Technology - BTech, Applied Electronics and Instrumentation
2010 — 2014
Sandeepani school of VLSI Design
Professional Development Course on VLSI Design and Verification - PG Diploma, VLSI
2018 — 2018
College of Engineering Trivandrum
Master of Technology - MTech, Micro & Nanoelectronics
2015 — 2017
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