Vedant Bansal
RTL Design Engineer @ Intel | BITS Pilani EEE 24\'
- Role
- Soc Logic Design Engineer at Intel
- Location
- Chandigarh, IN
- LinkedIn followers
- 500 followers
Information TechnologyView LinkedIn profile
About Vedant Bansal
I completed my Bachelor\'s in Electrical & Electronics Engineering from BITS Pilani, Pilani Campus in 2024. I\'m currently working as a SoC Logic Design Engineer (RTL Design Team) at Intel Foundry Services (IFS) group in Intel, Bangalore.
Experience
Soc Logic Design Engineer
Jul 2024 — Present · Bengaluru, IN
Education
Birla Institute of Technology and Science, Pilani
Bachelor of Engineering - BE, Electrical and Electronics Engineering
2020 — 2024
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