Ved Prakash Gupta

About Ved Prakash Gupta

16+ years of extensive experience in Physical design taped out multiple designs in 90/45/32/28/20/14/10/7/5 nm technology. Currently working on AMD Server Team, contributing FCT setup, FC clock closure, tile closure work from netlist to gds2. In the previous project(Server Chip) worked on DRC/LVS/timing closure for most critical tiles on entire chip. Expertise in low power designs and leading low power team for AMD Bangalore site 3 years of experience in graphics and APU (combined CPU an GPU) chips. Worked for graphics chip with 1.3 million+ gate count have high level of 20lpm design challenges. Having all industry level tool expertise including ICC2, ICC, Encounter, Primetime, MVRC, VSI,design compiler etc. Well versed with the complete Gate level Netlist to GDSII design flow, participated in all stages of the design. Participated in the top/block level full chip timing closure (STA) of multi-million gate ASICs. Participated in the successful tape-out of two ASICs. Involved in the physical design (floor planning, place route, CTS) of various ASICs. Well versed with timing analysis, physical design, synthesis, parasitic extraction, LVS/DRC.Specialties: ASIC Design Flow and Methodology Synthesis Floor plan & Power Planning Placement & Placement Optimization Clock tree synthesis Routing and Routing Optimization Design for Manufacturing Issues Physical Verification Timing Signoff MVRC LEC EM/IR

Experience

1. Principal Engineer

   Marvell Technology

   Oct 2023 — Present · Bengaluru, IN

   Working on next-gen IPs and Test Chip, which includes N+2 technology IPs.

Education

• ABV-Indian Institute of Information Technology and Management

  Master of Technology (MTech), VLSI Design

  2006 — 2008

• Uttar Pradesh Technical University

  Bachelor of Technology (BTech), Electrical, Electronics and Communications Engineering

  2002 — 2006

Skills

• Physical Design
• Clock Tree Synthesis
• Floorplanning
• Timing Closure
• Drc
• Static Timing Analysis
• Route
• Parasitic Extraction
• Vlsi
• Asic
• Physical Verification
• Lvs
• Mvrc
• Lec
• Em/Ir
• Cmos
• Integrated Circuit Design
• Low-Power Design
• Logic Synthesis
• Primetime
• Verilog
• Perl
• Routing
• Application-Specific Integrated Circuits (Asic)
• Design Rule Checking (Drc)