Vatika Vardhan Chaurasia

About Vatika Vardhan Chaurasia

Design Engineer with 8 years of Industry Experience in VLSI design. Skills • Auto Place & Route (APR) using Synopsys Fusion Compiler, ICCompiler 2 and Cadence Innovus• Static Timing Analysis using Primetime • Low Power Design Strategies • Scripting in Python, TCL • RTL Design using Verilog & System Verilog • RTL Synthesis flow using Synopsys DC Compiler and Cadence Genus • Design & Simulation of mixed signal circuits (CMOS)Contact me on v••••••••@gmail.com for relevant opportunities.

Experience

1. Design Automation Engineer

   Intel

   Jan 2019 — Present

   1) Worked on designing and validating the reference backend flows from Synthesis through Static Timing sign – offs using both Synopsys and Cadence tools. 2) Have designed regression testing flows and worked on validation plan. 3) Worked on several automations for testcase generations and metric calculations in python. 4) Developed various testcases such as integration and low power testcases for ASIC Design Flows. 5) Creating/Supporting vendor specific techfiles/techlef for PDK. 6) Working with other collateral teams to find root cause of the problem and driving solution to the issue. 7) Used ICValidator and Vendor specific verification tools to determine if it’s a collateral issue, flow issue or a techfile issue.

Education

• Jagat Taran Golden Jubilee, Allahabad

  Intermediate, PCM

  1996 — 2010

• Arizona State University

  Master of Science (MS), Electrical Engineering

  2017 — 2018

• Dr. A.P.J. Abdul Kalam Technical University

  Bachelor’s Degree, Electronics and Communications Engineering

  2010 — 2014

Skills

• Digital Circuit Design
• Plc
• Microsoft Office
• Vlsi
• C
• Powerpoint
• Microsoft Excel
• Databases
• Tableau
• Verilog
• Data Analysis
• C++
• Sql
• Business Objects
• Informatica
• Pl/Sql
• Microsoft Word
• Microsoft Powerpoint
• Java
• Talend
• Matlab
• Research
• Scada