Vatsal Dwivedi
Senior Verification Engineer @Arm
Cambridge, GB
EMAILS
MOBILE NUMBERS
+91 *********19
Signup · Get unlimited contacts
WORK HISTORY
Oct 2024 — Present
Senior Verification Engineer @Arm
View department →
Cambridge, GB
EDUCATION
2012 — 2014
Manipal Institute of Technology
Master of Science - MS, Tech; VLSI Design; Information Science
2004 — 2006
New Look
HSC; Sr. Sec, science
2007 — 2011
D.Y.PATIL College of Engineering University of PUNE
BE, Electronics & Tele Communication
2002 — 2004
Vidhya Niketan School
10th, Science
SKILLS
Static Timing AnalysisDigital ElectronicsUvmRed Hat LinuxVerilogPerlFunctional VerificationCMicrosoft OfficeVlsiSystemverilogWindows 7LinuxModelsim
ABOUT VATSAL DWIVEDI
Experienced Verification Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, and verilog. Masters in VLSI Design; from Manipal Academy of Higher Education (MAHE).
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.