Vaseemkhan B.
Sr Lead Engineer @ Qualcomm | Ex - Xilinx Inc
- Role
- Senior Lead Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Vaseemkhan B.
Expertise in Developing UVM, System Verilog based Testbench from scratchSkilled at Developing High level Test-plan(HVP), Test-cases, Track and Debug bugs in Design- Good knowledge of Digital Design in gate Level- Proficient In ASIC / SOC product development flows - Skilled in coverage driven verification methodologies ( Code & Functional coverage )- Skilled In debugging RTL, ROM Source code & Gate level netlists - Good Experience in Verification Methodologies such as SV (System Verilog), UVM (Universal Verification Methodology), Assertions and Coverage and C based verification. Personal qualities - Good team worker as well as an independent worker. Keen to learn new things and adopt to new challenges- Adaptable to any kind of environment and can work under pressure, keen observer and easy to go nature, passionate learner - Excellent analytical and communication skills.Field of Interest VLSI - RTL Design, ASIC/SOC Verification Verification - Constrained random verification, Coverage driven verification, Functional/Protocolverification, Assertion based verification, Regression Mechanism, clear case, Perfoce. Protocols - SPI protocol, AMBA-AXI-3, 4, 4-lite, DDR4 (MEMORY CONTROLLER), Ethernet lite 802.3, H264/265 Decoder & Encoder, VP8, VP9 Encoder & Decoder, MPEG2D. Security related algorithms etc.Technical SkillsHDLs Verilog HVL SystemVerilogTB Methodology UVMSOC Verification - Embedded C.Boot ROM Verification.Security Verification.Protocols ( Expert in AMBA Buses)- AHB,APB, ahb2apb BRIDGE, AXI-3,4,AXI-lite, SPI,JTAG,Ethernet lite.Scripting Language PYthon, Makefile, Shell scripting.EDA Tool Synopsys VCS, Verdi, DVE, Aldec-Riviera Pro, Questa Sim, Xilinx ISE, Modelsim, Vivado.Language C, Embedded COS Linux, WindowsSkills Functional Verification, Assertion based Verification, Constrained-random Verification,Coverage Analysis, ROM Code. System level verification.Thank you for your time! Your\'s Honestly, VASEEM v••••••••@gmail.com+91••••••••04
Experience
Senior Lead Engineer
Dec 2023 — Present · Bengaluru, IN
Education
M S Engineering College, BANGALORE
Bachelor of Engineering (B.E.), Electronics and Communications Engineering
2012 — 2016
Seventh-Day Adventist school.
Higher Secondary, Biology-maths
2000 — 2012
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