Vaseekaran Rajagopal
Fellow @ AMD | CPU Core Design
- Role
- Fellow Silicon Design Engineer at AMD
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Vaseekaran Rajagopal
Fellow CPU Design Engineer at AMD, with 24+ years of semiconductor industry experience.My core competencies include CPU core design, debug, verification and validation, and a deep understanding of computer architecture, microarchitecture, and their interplay with OS, BIOS, firmware, Hypervisors, and application software. I greatly enjoy collaborating with cross-functional teams to solve complex technical challenges
Experience
Fellow Silicon Design Engineer
Jan 2007 — Present · Austin, TX, US
Current: CPU Core Design | MicrocodePrevious: CPU Cores DV Architect- Focus: Silicon Validation, Emulation, Core DebugCPU Core Silicon Validation Lead- Zen5CPU Core Verification Debug Lead- Zen, Zen2, Zen5CPU Core Verification Engineer-Bulldozer family, Zen, Zen2, Zen5CPU Core Silicon Debug Engineer-Bulldozer family, Zen, Zen2, Zen3, Zen5
Education
The University of Texas at Austin
Unfinished. MS
2018 — 2019
University of Madras
Bachelor of Engineering
1996 — 2000
Skills
- X86
- Pcie
- Verilog
- X86 Assembly
- Asic
- Virtualization
- Dft
- Cache Coherency
- Functional Verification
- Debugging
- Operating Systems
- Formal Verification
- Microarchitecture
- Soc
- Dfd
- Performance Analysis
- Low-Power Design
- C
- Bios
- Microprocessors
- Rtl Design
- Logic Design
- Vlsi
- C++
- Perl
- Processors
- Silicon Validation
- Uvm
- Microcode
- Timing Closure
- Computer Architecture
- Systemverilog
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