Vasavi S

Experience

1. Physical Design Trainee

   Maven Silicon

   May 2025 — Present · Bengaluru, IN

   Completed Digital Electronics and Verilog HDL training at Maven SiliconCurrently undergoing VLSI Physical Design trainingLearning the ASIC design flow: floorplanning, placement, CTS, routing, and timing analysisHands-on practice with EDA tools (Synopsys & Cadence)Exposure to low-power design methodologies, physical verification, and timing closureStrong foundation in logic design, Verilog coding, and Static Timing Analysis (STA)Passionate about VLSI and eager to build a career in the semiconductor industry

Education

• Visvesvaraya Technological University

  Bachelor of Engineering - BE

  2021