Roopak Vasa

About Roopak Vasa

13+ years in memory circuit design and verification at Micron, Synopsys, Invecas, and STMicroelectronics.Deep expertise in bit cell analysis, process entitlement, write and read margin, timing race margin analysis, sense amplifier analysis, level shifter analysis, verilog equivalence checks, timing, leakage, and power characterization, and fullRC instance at speed simulations.Successfully led the team in the DDR5 test mode verification, SRAM/RF circuit designs across FinFET, FD-SOI, and legacy nodes.

Experience

1. Principal Engineer Memory Circuit Design Verification

   Micron Technology

   Apr 2024 — Present · Hyderabad, IN

   Managed and coordinated tasks within the Hyd TMTB Verification team, for the first 3D stacked DDR5 chip in 160 series, ensuring timely completion of all test modes and closing 238 test mode JIRA tickets. Conducted hands-on sessions to teach MRUN flow, mentored the team in writing the IWM script and debugging it using Py debugger. Presently leading the TMTB verification section for the first alpha chip for DDR5 in 170 series with 3D stack. Groomed the team for efficient written communication via emails and JIRA comments.

Education

• G. H. Patel College of Engineering and Technology

  B.E., Electronics and communication

  2006 — 2010

• Institute of Technology, Nirma University

  M.Tech., VLSI Design

  2010 — 2012

Skills

• Rom
• Circuit Design
• Memory Characterization
• Memory Design
• Characterization
• Memory
• Sram
• Simulations