Varun Kumar
SOC Timing Engineer
- Role
- System-on-chip Design Engineer at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
About Varun Kumar
Experienced System-on-Chip Timing Engineer with a demonstrated history of working in the semiconductors industry. Worked on cutting edge technology nodes in server family processors. Skilled in Static Timing Analysis, Timing closure and sign off, Hierarchical timing including IO budgeting for partitions, Clock domain crossing issues, Timing ECOs generation, Quality checks and DRV. Well versed with the concept of On-Chip Variation, Signal Integrity and different Timing Models. Experienced in TCL and Perl automation. Strong engineering professional graduated from Indian Institute of Technology, Bombay in Microelectronics specialization.
Experience
System-on-chip Design Engineer
May 2022 — Present · Hillsboro, OR, US
Education
Institution of Engineers of India (IEI), Kolkata
Bachelor of Engineering - BE, Computer Science
2008 — 2012
Indian Institute of Technology, Bombay
Master of Engineering - MEng, Electrical and Electronics Engineering
2014 — 2016
Institution of Engineers of India (IEI), Kolkata
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
2012 — 2014
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