Varun Patial

About Varun Patial

Professional Experience of 9 years with Hands on experience in complete layout flow from floor planning to GDSII tape-out.* Have strong experience in full custom layouts for high speed SERDES, DDR, PLL, Frequency Synthesizer\'s, Clock networks and Custom Standard Cells.* Have strong experience in various Chip and IP verifications like DRC, LVS, ERC, DFM, ESD, Latch-up, Antenna, WPE, EM, IR drop, Self-Heat and FIT.* Worked on BULK CMOS technologies for various foundries like TSMC, Samsung and UMC.* Worked on various technologies like 2nm,4nm 5nm, 7nm, 16nm, 28nm, 40nm and 180nm.* Knowledge on Circuit design/simulations (Bias circuit, Current Mirrors and Diff amp).* Knowledge on LEF/Abstract views.* Automation by using Cadence-SKILL & PERL to improve the productivity.* Good leading skills to complete the project successfully on-time with great quality.* Good knowledge on Deep sub-micron issues like DFM, Well Proximity and LOD.* Strong Academic Experience of 3.7 years in Teaching Field for Core Electronics Subjects (Analog/Digital Design, Microelectronics etc.)

Experience

1. Technical Lead (Analog Layout)

   IBM

   Aug 2025 — Present · IN

Education

• Himachal Pradesh University

  Master of Business Administration - MBA, Human Resources Management and Services

  2012 — 2014

• Thapar University Patiala

  M.Tech, VLSI DESIGN AND CAD

  2010 — 2012

• I.E.E.T Baddi

  Bachelor of Technology (B.Tech.), Electronics and Communication

  2004 — 2008

Skills

• Cadence
• Perl
• Eda
• Xilinx
• Compiler Optimization
• Verilog
• Integrated Circuit Design
• Standard Cell Layout Design
• P Cell
• Vlsi
• Analog
• Rf
• Vhdl
• Scripting
• Analog Layout Design