Varun Karthik Surapaneni
PDV Engineer at Apple | UCSD | BITS Pilani Goa
- Role
- Physical Design Verification Engineer at Apple
- Location
- San Diego, CA, US
- LinkedIn followers
- 500 followers
Experience
Physical Design Verification Engineer
Jul 2024 — Present · Santa Clara, CA, US
I work with the SoC PDV team to work on fullchip Bumps and RDL planning and execution ensuring that we meet all the design requirements.I also work on full chip ESD clamp placements and positioning to ensure that the entire die is ESD compliant and there is no ESD risk.
Education
Birla Institute of Technology and Science, Pilani K.K Birla Goa Campus
Bachelor of Engineering - BE, Electrical and Electronics Engineering
2018 — 2022
UC San Diego
Master of Science - MS, Computer Engineering
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