Varun Ande

Senior Asic Verification Engineer @Axiado Corporation

Worked closely with Design and Architecture teams to review specifications for Ethernet subsystem (includes 4x1G and 1x10G MAC) and extracted features and define verification plan including coverage. Developed test plan for module level testing and executed through testbench development, directed/constrained random test generation, assertion-based verification, failure analysis and resolution, and coverage analysis and closure. Developed AXI Driver to generate stimulus for module level testing Testing the DUT with complex testcases involving the control and data paths in verification platforms like UVM methodology, system Verilog techniques, bare metal code in software environment on Linux machines. Debug with behavioral simulation using Synopsys VCS with Bare metal C code. Converted Module level tests from the Vendor to full chip environment and tested Ethernet MAC and EIP-197 for basic functionality with the SystemVerilog and UVM. Verified block level and full chip level DUT using emulation on Veloce and FPGA prototyping on Dini and Zynq boards.