Varshini N
RTL Design Engineer, Texas Instruments
- Role
- Rtl Design Engineer at Texas Instruments
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
Experience
Rtl Design Engineer
Jul 2023 — Present · Bengaluru, IN
Managing SoC integration - Managing QC checks and the design of multiple IPs- Proficient in industry-standard tools like Cadence JasperGold for quality checks, including Lint and Clock Domain Crossing (CDC) analysis- Experienced in area synthesis for various IPs using Cadence Genus, ensuring optimal design performance while considering physical design constraints- Hands-on experience in Boundary Scan Verification as part of adjacent work responsibilities.
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