Varatharajan Bose

About Varatharajan Bose

ASIC RTL Design, Verification and Implementation Engineer with 23+ years of VLSI industry experience including:Specialties: ASIC/FPGA Front End RTL Design and VerificationMicro Architecture, RTL coding and SoC Integration,Low Power Design and implementationSystem Verilog UVM based verifcation Methodologies Synthesis and (STA)Timing Analysis,IP Integration on SoC, quality check Lint, CDC, LEC, Power analysisFPGA prototyping, Emulation, Pre-Silicon and Post-Si validation, Board level debugSuccessfully executed many turnkey projects and significantly contributed for many ASIC / SoC tapeouts from 5nm process technology nodes

Experience

1. Principal Engineer

   Infineon Technologies

   Mar 2023 — Present · Bengaluru, IN

   Principal Design and Verification Engineer in Memory Solution group

Education

• Madurai Kamaraj University

  BE, Electrical and Electronics

  1997 — 2001

Skills

• Arm
• Modelsim
• Logic Synthesis
• Fpga Prototyping
• Fpga
• Asic
• Vhdl
• Timing Closure
• Rtl Verification
• Embedded Systems
• Eda
• Architecture
• Component Verification
• Ncsim
• Static Timing Analysis
• Fpga Emulation
• Debugging
• Rtl Design
• Emulation
• Tcl
• Soc
• Vlsi
• Rtl Coding
• Functional Verification
• Fpga, Syntheis
• Architectures
• Pre Silicon and Post Silicon Validation
• Archtecture Design and Implementation
• Systemverilog
• Verilog
• Integrated Circuit Design