Vandna Dhingra

About Vandna Dhingra

Working as a Back-end engineer for Physical Design department. Have worked on high-frequency chip closure at lower technology nodes (45nm and 16nm). Hands-on practice on the flow RTL to GDS-II using EDA tools.Key Experiences on- Synthesis : Hands-on experience on Design-Compiler with IP hardening by RTL hacking, reducing power and area at synthesis using SPG and WLM modelling- Floor-planning : Good grasp of board-level requirement and thus understanding logical connectivity s so as to prepare a refine placement stratergies - Placement and Routing : Worked on TIMING vs CONGESTION trade-off for SoC with huge logic size and attained successful closure. Awareness of CCD and NON-CCD flow at CTS and knowledge of building standalone H-TREE- EDA capability: Design-Compiler( Synopsys ), STAR RC, Innovus( Cadense ), ICC2 ( Design Planning)- Strong understanding of Physical Design Flow and its correct applications- Knowledge of TCL based scripting and flow development- Always Interested to learn more and become more efficient- Strong interpersonal, communication and management skills- Strong debugging and problem solving skills

Experience

1. Staff Engineer

   Arm

   Aug 2025 — Present · Bangalore Urban, IN

Education

• MAHESHWARI VIDYAPEETH

  SSC, SCIENCE

  2009 — 2013

• Nirma Institute Of Technology

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

  2013 — 2017

Skills

• C
• Teaching
• Basic Html
• Microsoft Office
• Vlsi
• Online Advertising
• Research
• Data Management
• Hdl Programming
• Basic Java
• Microsoft Excel
• Powerpoint
• Public Speaking
• Event Planning
• Training
• Anchoring
• Microsoft Word
• Social Media
• Java
• Leadership
• Iot
• Event Management
• Marketing
• Management
• C++
• Microsoft Powerpoint