Vanaparthi Soujanya
Physical Design Engineer (Fresher) | RTL-to-GDSII | Floor-planning, Placement, CTS, Routing | Cadence Innovus
- Role
- Physical Design Engineer Intern at Chipxpert
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Vanaparthi Soujanya
Entry-level Physical Design Engineer with hands-on experience in RTL-to-GDSII flow for ASIC designs. Trained in floorplanning, power planning, placement, CTS, routing, and sign-off using Cadence Innovus.Experienced in timing analysis and basic timing closure, including setup/hold violation fixing and congestion awareness. Familiar with physical cells such as tap cells, end caps, well taps, and tie cells for DRC-safe layouts.Strong foundation in VLSI fundamentals, CMOS concepts, and digital electronics. Skilled in Tcl scripting to automate PD tasks, report generation, and analysis.Actively seeking an entry-level Physical Design / ASIC Backend Engineer role in a semiconductor product company.
Experience
Physical Design Engineer Intern
Jul 2025 — Present · Hyderabad, IN
Working on RTL-to-GDSII Physical Design flow using Cadence Innovus.Hands-on with floor planning, power planning, placement, CTS, and routing.Performed timing analysis and assisted in setup/hold timing closure.Worked with tap cells, end caps, and well taps for latch-up prevention.Used TCL scripts to automate PD reports and checks
Education
KAMALA INSTITUTE OF TECHNOLOGY & SCIENCE
B.Tech, Electronics and communication engineering
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