Vamsi Puritipati
VLSI Design Verification Engineer | Emulation | Top DV | Qualcomm | DFT | Ex-Intel
- Role
- Senior Design Verification Engineer at Qualcomm
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Vamsi Puritipati
Programming/HDL Languages: Verilog, SystemVerilog, C, C++• EDA tools: Mentor Graphics Veloce Emulator, Questasim, Verdi, VCS• Scripting: Perl, TCL• Verification Methodology: UVM
Experience
Senior Design Verification Engineer
Jul 2021 — Present · Santa Clara, CA, US
Working on TOP level verification for Snapdragon Video coresWorking on creating/sanitizing/debugging the top level emulation builds(Veloce/VIPR) and delivering them for firmware bring-upWorking with bring-up of emulator platforms, digital design, verification, debugging, and waveformDevelopment of all aspects of hardware emulator implementation, with emphasis on design partitioning, synthesis, place and route, timing analysis & run time performance.Drive debug failures on emulator using latest technologies. Work with designers and SW driver team for testplan and debug.Work with tool vendors and push the methodology to improve the area/performance of the synthesized FPGA RTL.Work on third-party IP integration and system-level debugging.System level RTL simulation & design verification.Debug functional and timing models. viewers
Education
Portland State University
Master's degree, Electrical & Computer Engineering, ASIC Design Verification/ Validation
2017 — 2018
Shanmugha Arts, Science, Technology and Research Academy
B.Tech, Electronics and Communications Engineering
2011 — 2015
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