Vamsi Krishna Vangala

About Vamsi Krishna Vangala

16+ years of experience in Physical Verification (DRC/LVS/DFM), reliability and Layout Parasitic Extraction (LPE) flow• DRC/LVS Runset development and customer support on Mentor Graphics Calibre Synopsys ICV/Hercules and Magma Quartz.• Strong experience in evaluation/qualification of LPE tools like Synopsys StarRC, Cadence QRC• Worked across various technologies (45nm to 5nm) for various foundries (TSMC, Common Platform/Global Foundries/IBM, Samsung).• Supported internal and external customers both on-site and off-site in the role of Product Engineer.• Strong role in training, selection and mentoring interns/new hires in the team.Skill set:PV tools : Mentor Graphics Calibre DRC/LVS/DFM/PERC, ICValidator LVS/DRC (Physical verification tool of Synopsys)Scripting languages : Perl, Tcl/Tk, SKILL and Shell programmingParasitic Extraction: Synopsys StarRC(Synopsys Layout Parasitic Extraction tool)Layout :Virtuoso (Cadence), Titan (Magma), CustomDesigner, Calibre DESIGNrev, ICWBEV (Synopsys)Misc Flows: Pre and post layout simulation, EM and IR drop

Experience

1. Cad Engineer

   Intel

   Sep 2020 — Present · Bengaluru, IN

   Physical verification/sign-off CAD for advanced nodes (AMS/AIP)Tools/Flows/Methodology for back end flows

Education

• Indian Institute of Technology, Kharagpur

  BTech and MTech (5yr Integrated), Electrical

  2002 — 2007

Skills

• Integrated Circuits (Ic)
• Physical Design
• Physical Verification
• Perl
• Eda
• Baby Showers
• Scripting
• Hercules
• Shell Scripting
• Very-Large-Scale Integration (Vlsi)
• Static Timing Analysis
• Lvs
• Ic
• Icvalidator
• Drc
• Tcl
• Quality Assurance
• Debugging
• Layout Versus Schematic (Lvs)
• Parasitic Extraction
• Babysitting
• Calibre
• Vlsi
• Soc
• Asic
• Design Rule Checking (Drc)
• Semiconductors