Vamsi Emani

About Vamsi Emani

I’m a Physical Design engineer with hands-on experience driving RTL-to-GDSII flows at advanced technology nodes, currently working as a GPU Physical Design Methodology Engineer Intern at Intel. My work focuses on building, optimizing, and debugging scalable physical design flows that improve PPA, runtime, and design convergence across complex partitions.At Intel, I’ve contributed to both Cadence and Synopsys-based flows at TSMC 2nm and Intel 18A, working across synthesis, placement, CTS, routing, and timing closure. I’ve helped enable tool migrations, integrated AI-driven optimization (DSO.ai), and developed automation for timing analysis and ECO optimization—achieving measurable improvements in TNS, area, power, and runtime. I also enjoy diving deep into tricky issues like congestion hot spots, PVT mismatches, DRC violations, and flow inconsistencies, and turning them into robust methodology improvements.My academic and project work complements this industry experience, including zero-skew clock tree synthesis, STA tool development using NLDM models, and multiple full RTL-to-GDSII tapeout-style flows in TSMC 16nm. I’m comfortable across the stack—from Verilog and algorithms to signoff with PrimeTime, Calibre, and power integrity analysis.I’m passionate about building clean, reusable physical design methodologies and working on cutting-edge silicon that scales. Always happy to connect with others working in physical design, VLSI, and semiconductor engineering.

Experience

1. Gpu Physical Design Methodology Intern

   Intel

   Jun 2025 — Present · Folsom, CA, US

Education

• National Institute of Technology Arunachal Pradesh

  Bachelor of Technology - BTech, ELECTRONICS AND COMMUNICATION ENGINEERING

• Kendriya Vidyalaya

  School

• University of Minnesota

  Master's degree, VLSI