Vamsee Pulugulla
RTL Design Engineer at Apple
- Role
- Rtl Design Engineer at Apple
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Rtl Design Engineer
Feb 2023 — Present · Cupertino, CA, US
Education
Maharishi Vidya Mandir Senior Secondary School
High School
2007 — 2012
SRM University
Bachelor of Technology (B.Tech.)
2012 — 2016
Arizona State University
Master of Science (M.S.)
2016 — 2018
Skills
- H-Spice
- Rtl Design
- Static Timing Analysis
- Matlab
- Simulink
- C
- C++
- Sql
- Labview
- Arduino
- Autocad
- Solidworks
- Catia
- Siemens Nx
- Unix
- Verilog
- Perl
- Shell Scripting
- Cadence Virtuoso
- Cadence Spectre
- Hercules
- Modelsim
- Cadence Encounter
- Synopsys Primetime
- Synplify Pro
- Tcl
- Cadence Virtuoso Layout Editor
- Cadence Icfb
- Synopsys Tools
- Rtl Coding
- Rtl Verification
- Systemverilog
- Python
- Very-Large-Scale Integration (Vlsi)
- Vlsi Cad
- Application-Specific Integrated Circuits (Asic)
- Microsoft Office
- Microsoft Excel
- Microsoft Word
- Nand
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