Vaishnavi J.
Process Engineering Intern @Lam Research
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WORK HISTORY
Process Engineering Intern @Lam Research
Tualatin, OR, US
Project 1: Process development of electrodeposition of barrier metal films at Cu bump-solder interface for microbump packaging - Contributing to advanced packaging research focused on challenges in intermetallic compound (IMC) formation due to thinning Ni barrier at microbump interconnects in HBM dies – exploring alternate novel alloy barrier films - Conducting Sabre 3D tool-level studies - Gaining experience in wafer inspection/qualification post electrodeposition, process demonstration on customer wafers- Prepared and implemented a thorough benchtop electrolyte qualification study - Leading the development of pulse-electrodeposition protocol for alloy electrodepositionProject 2: Investigated spontaneous metal deposition at the wafer lip seal in the Sabre 3D tool (Wafer-rinsing step, Sn-based solder bath)- Probed the root cause and proposed the preventive measures for undesired metal deposition to minimize lip seal replacements for customersProject 3: Assisted in screening additives for the bottom-up filling of Cu electrodeposition in Redistribution Layer (RDL) Vias
EDUCATION
Case Western Reserve University
Doctor of Philosophy - PhD
Amrita Vishwa Vidyapeetham
Bachelor of Technology
ABOUT VAISHNAVI J.
Process Engineer in Wafer Level Packaging with expertise in electrodeposition…
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