Vaishnavi Sanjeev
Microsoft • Georgia Tech • Synopsys
- Role
- Design Verification 2 at Microsoft
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Vaishnavi Sanjeev
Completed an MS degree in Electrical and Computer Engineering at Georgia Tech.Silicon Engineer with 5+ years in the semiconductor industry. Constrained Random Verification of IPs using SV/UVM. Everything from Testplan, Verification Plan to coverage closure including testbench development (stimulus and scoreboard).
Experience
Design Verification 2
Aug 2024 — Present
Education
Georgia Institute of Technology
Master of Science - MS, Electrical and Computer Engineering
PES University
Bachelor's degree, Electronics and Communications Engineering
2015 — 2019
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