Vaishnavi Jaiswal
Senior Design Engineer at Analog Devices | Ex-Intel | IIT Kharagpur
- Role
- Senior Design Engineer at Analog Devices
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Vaishnavi Jaiswal
RTL Design Engineer with 4 years of experience in ASIC Design, SoC Design, Microarchitecture analysis and design of blocks. Proven Hands-on experience in RTL Coding and Validation using Verilog for block level implementations. Demonstrated expertise in Lint, CDC/RDC,LEC checks to ensure delivery of high quality RTL. Proven ability to seamlessly collaborate with cross functional teams to successfully resolve design challenges and achieve project objectives.
Experience
Senior Design Engineer
Aug 2023 — Present · Bengaluru, IN
Education
Indian Institute of Technology, Kharagpur
Master of Technology - MTech, Visual Information and Embedded system engineering
2019
Institute of Engineering and Technology, DAVV,Indore
Bachelor of Engineering, Electronics and Telecommunication Engineering
2013 — 2017
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