Vaishnavi G Urs
Analog Mixed Signal Verification Engineer @ Allegro MicroSystems | Specializing in Analog-Mixed Signal design Verification | MS in Electrical Engineering.
- Role
- Analog Mixed Signal Verification Engineer at Allegro MicroSystems
- Location
- Tempe, AZ, US
- LinkedIn followers
- 500 followers
About Vaishnavi G Urs
Analog Mixed Signal Verification Engineer with a strong focus on chip-top level verification and methodology. Proven expertise in verification planning, and ensuring comprehensive coverage of design requirements. Experienced in running regression tests to validate design robustness and ensure efficient, bug-free tape-outs. Passionate about leveraging a broad technical background and cross-functional collaboration to drive team success and achieve organizational goals.
Experience
Analog Mixed Signal Verification Engineer
Jun 2023 — Present · Manchester, NH, US
Education
Ira A. Fulton Schools of Engineering at Arizona State University
Master's degree, Electrical and Electronics Engineering
Arizona State University
Masters, MS in Electrical and Electronics Engineering
2021 — 2023
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