Vaishnavi Arikala
Senior Silicon Design Engineer at AMD
- Role
- Senior Silicon Design Engineer at AMD
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
Experience
Senior Silicon Design Engineer
Nov 2025 — Present · Austin, TX, US
roles and duties as a Formal Verification CAD Engineer:Owns and maintains mechanisms for safely handing off RTL from verification flows into construction flows. Which involves developing and enhancing complex perl and python scripts. Owns and maintains mechanisms for performing differential analysis of register mapping files between LEC stages generated by industry standard tools to identify RTL modifications across the LEC flow stages. Conducts LEC flow setup reviews for mutliple project tapeouts. Executes and maintains regression test suites for validation of LEC tools, flow updates and debugs failures in regression. Provides technical support to internal project teams on flow setup, debug and troubleshooting reported tool or flow issues. Automates CAD flows ton simplify the Logical Equivalence Check setup process and minimize manual configuration requirements. Maintains comprehensive technical documentation for flow setup procedures.
Education
Arizona State University
Master of Science - MS, Electrical, Electronics and Communications Engineering
CVR College of Engineering, Hyderabad
Bachelor's of technology, Electronics and Communications Engineering
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