Vaidhyanathan M
IP Design Verification, Intel | Ex-Synopsys | Manipal School of Information Sciences
- Role
- Ip Design Verification Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Vaidhyanathan M
ASIC Design Verification Engineer with 3.5 years of experience in IP verification- HDL : System Verilog, Verilog- HVL : System Verilog, UVM- Working with High Speed Interface Protocol : UFS HCI, MIPI UniPro, MIPI MPHY- Bus Protocols : APB- Tools : VCS, Verdi, VC-NLP (Low power)- Scripting : Shell, Perl and Python.Current work focused in verifying Inter-operability of MIPI MPHY v4.1/v5.0 IP with MIPI UniPro v1.8/v2.0 and UFS v3.0/v4.0 IPs.
Experience
Ip Design Verification Engineer
Jun 2024 — Present · Bengaluru, IN
Verification of I2C/SPI/UART/I3C in a Subsystem.
Education
Sadvidya Composite PU college
Physics/Chemistry/Maths/Electronics
School of Information Science, Manipal
ME, VLSI Design
2018 — 2020
National College, Basavanagudi, Bangalore-4(Autonomous)
Physics/Chemistry/Maths/Electronics
VIDYA VIKAS INSTITUTE OF ENGINEERING AND TECHNOLOGY
Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering
2014 — 2018
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