Utkarsh Agrawal
Chiphead | PnR Dragon Slayer (11+ yrs) | RTL-to-GDSII for 5/4/2nm SoCs | PPA Expert
- Role
- Senior Staff Engineer at Samsung Semiconductor
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Utkarsh Agrawal
Turning RTL chaos into silicon-ready SoCs with 11+ years of experience, delivering tape-outs from deep-submicron nodes (5/4/2nm) for complex low-power and high-performance designs.• Drives full RTL-to-GDSII implementation, including hierarchical physical architecture, Physical Synthesis, robust floor-planning, power grid design, placement, Clock Tree Synthesis (CTS) & routing, timing closure, advanced low-power techniques (UPF/CPF, power-gating, DVFS), and final Physical Verification (DRC/LVS) sign-off.• Proven track record in sign-off, achieving Timing IR-drop, EM, and Signal Integrity (SI) closure, resolving complex corner cases and tape-out bottlenecks.• Hands-on with Synopsys Fusion Compiler and Cadence Innovus, leveraging TCL/Python scripting to optimize design flows, improve efficiency, and deliver silicon-ready results under aggressive schedules.
Experience
Senior Staff Engineer
Mar 2024 — Present · Bengaluru, IN
Education
Moral Convent H.S. School
Intermediate, PCM
2007 — 2009
Ebenezer Sr Sec School
High School
1997 — 2007
ITM UNIVERSITY, GWALIOR
Bachelor of Engineering (B.E.), Electronics and Communications Engineering
2010 — 2014
Skills
- Clock Tree Synthesis
- Circuit Design
- Public Speaking
- Static Timing Analysis
- C++
- C
- Microprocessors
- Tcl-Tk
- Place & Route
- Shell Scripting
- Floorplanning
- Physical Design
- Physical Verification
- Assembly Language
- Microsoft Office
- Vlsi
- Asic
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