Mohammad Mannan

About Mohammad Mannan

Product Development Engineer with 10+ years in semiconductor R&D and manufacturing, specializing in analog/mixed-signal IP validation, NPI, and yield optimization. Proven track record of driving prototype-to-production transitions, leading cross-functional teams, and influencing product roadmaps through data-driven decision-making and robust validation strategies. • My expertise spans PLL, LDO, BGR, RNG, DDR, and DTS IPs, where I bridge circuit design, silicon-to-simulation correlation, and product engineering to deliver reliable and manufacturable solutions.• Led New Product Introduction (NPI) efforts, including wafer sort analysis, yield optimization, and validation strategy development, ensuring smooth transition from prototype to mass production. Skilled in data-driven problem solving with tools such as JMP, Python, MATLAB, SQL, and SPC/FMEA methodologies, I excel at identifying root causes, improving yield, and accelerating time-to-market.• Skilled in high-volume device parametric data analysis, statistical modeling, post-silicon validation methodologies, product development, and yield improvement with a strong device physics background •Experienced in fab process engineering, precision etch recipe development, module maintenance, upgradation, and technology transfer.• Known for cross-functional collaboration with design, technology development, validation, and foundry teams, I bring a proven ability to translate device physics and process interactions into product-level insights that enhance performance, manufacturability, and reliability.• Passionate about advancing analog/mixed-signal technologies that enable the next generation of computing, AI, and semiconductor innovation

Experience

1. Technical Lead, Product Development, Testing & Validation for Google

   HCLTech

   Oct 2025 — Present · San Diego, CA, US

   As a Technical Lead supporting Google’s silicon development programs, I drive mixed-signal validation, debug, and first-silicon bring-up for next-generation ASICs. My role focuses on validating critical analog/mixed-signal IPs, developing automated test infrastructures, and collaborating closely with cross-functional design teams to ensure robust performance across PVT conditions.

Education

• University of South Carolina

  Doctor of Philosophy (PhD), Electrical and Electronics Engineering

  2012 — 2015

• Concordia University

  Master's in Applied Science ( M.A.Sc), Electrical and Electronics Engineering

  2009 — 2011

• Bangladesh University of Engineering and Technology

  Bachelor of Science (BSc), Electrical and Electronics Engineering

  1993 — 1998

Skills

• Matlab
• Pspice
• C++
• C
• Electrical Engineering