Urvashi Dhoot

About Urvashi Dhoot

As a Senior ASIC Engineer at NVIDIA with over seven years of industry experience, my expertise is rooted in static timing analysis and circuit analysis. By leveraging advanced EDA tools, I contribute to resolving critical chip timing violations and optimizing chip performance across various conditions. Being part of the ASIC PD team, I ensure alignment with STA sign-off conditions to support successful project outcomes. My work focuses on timing closure and precision, underscoring a commitment to delivering robust and efficient solutions for complex hardware design challenges.

Experience

1. Senior Asic Engineer Sta

   NVIDIA

   Feb 2019 — Present · San Francisco, CA, US

   static timing analysis and circuit analysis to resolve critical chip timing violations. • Execute engineering change orders to optimize chip performance across various conditions using EDA tools. • Collaborate with the ASIC PD team to align STA sign-off conditions, ensuring successful project outcomes.

Education

• Nagpur University

  Bachelor’s Degree, Electrical, Electronics and Communications Engineering

  2011 — 2015

• Modern Vidya Nikeran Sr. Sec. School

  High School

  2005 — 2011

• University of Southern California

  Master’s Degree, Electrical and Electronincs Engineering, VLSI Design

  2015

Skills

• Synopsys Primetime
• Cadence Virtuoso
• Microsoft Office
• Very-Large-Scale Integration (Vlsi)
• 8051 Microcontroller
• Fpga
• Negotiation
• C
• Powerpoint
• Microsoft Excel
• Verilog
• Pspice
• Rtl Design
• Public Speaking
• Verdi
• Leadership
• Dbms
• Atp
• Static Timing Analysis
• Synopsys Tools
• C++
• Xilinx
• Computer Architecture
• Customer Service
• English
• Python
• Management
• Linux
• Analysis
• Perl
• Quantum Mechanics
• Microsoft Word
• Cadence Encounter
• Team Leadership
• Automatic Test Pattern Generation (Atpg)
• Teamwork
• Team Management
• Nanotechnology
• Dft
• Project Management